
PIC18F45J10 FAMILY
DS39682E-page 160
2009 Microchip Technology Inc.
REGISTER 16-3:
SSPxSTAT: MSSPx STATUS REGISTER (I2C MODE)
R/W-0
R-0
R0
R-0
SMP
CKE
D/A
P(1)
S(1)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP:
Slew Rate Control bit
In Master or Slave mode:
1
= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE:
SMBus Select bit
In Master or Slave mode:
1
= Enable SMBus specific inputs
0
= Disable SMBus specific inputs
bit 5
D/A:
Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P:
Stop bit(1)
1
= Indicates that a Stop bit has been detected last
0
= Stop bit was not detected last
bit 3
S:
Start bit(1)
1
= Indicates that a Start bit has been detected last
0
= Start bit was not detected last
bit 2
R/W:
Read/Write Information bit (I2C mode only)
In Slave mode:(2)
1
= Read
0
= Write
In Master mode:(3)
1
= Transmit is in progress
0
= Transmit is not in progress
bit 1
UA:
Update Address bit (10-Bit Slave mode only)
1
= Indicates that the user needs to update the address in the SSPxADD register
0
= Address does not need to be updated
bit 0
BF:
Buffer Full Status bit
In Transmit mode:
1
= SSPxBUF is full
0
= SSPxBUF is empty
In Receive mode:
1
= SSPxBUF is full (does not include the ACK and Stop bits)
0
= SSPxBUF is empty (does not include the ACK and Stop bits)
Note 1:
This bit is cleared on Reset and when SSPEN is cleared.
2:
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.